1. Field of the Invention
This invention relates to semiconductor integrated circuit devices, and more particularly, to a semiconductor integrated circuit implementing a desired function by providing a plurality of logic cells on a semiconductor substrate and connecting logic cells to each other.
2. Description of the Background Art
FIG. 10 is a diagram illustrating one example of a layout of a conventional semiconductor integrated circuit device employing standard cells. Referring to FIG. 10, standard cell rows 2 and interconnection areas 3 are alternately arranged on a semiconductor substrate 1. Each standard cell row 2 is formed of a plurality of standard cells arranged in a lateral direction. Each standard cell comprises a fundamental logic cell such as a NAND, a NOR, a counter and a latch. Each standard cell is selected so that respective height in a longitudinal direction is the same.
Generally, the above described standard cells are automatically arrayed and interconnected by an automatic design system using CAD (Computer Aided Design). That is, the automatic design system selects the standard cells necessary to perform a desired function from among plural kinds of standard cells previously registered within a data file and arranges them automatically on a semiconductor substrate 1. Subsequently, the automatic design system provides prescribed interconnections for each standard cell arranged regularly on semiconductor substrate 1. As a result, a semiconductor integrated circuit device having desired functions is automatically designed. The aforementioned operation of arranging and interconnecting standard cells is performed according to an automatic arranging and interconnecting program.
As described above, when a semiconductor integrated circuit device is designed by the automatic arranging and interconnecting program, how long the interconnection length of a specific node will be is known only after the automatic arranging and interconnecting is performed, and therefore, each standard cell is designed to have sufficient output driving capability even in the worst case (the case in which an interconnection length becomes the longest). However, in a case where an interconnection length is implemented only with a short interconnection length which does not reach a length in the worst case, as a consequence of the automatic arranging and interconnecting, output driving capability of each standard cell becomes greater than necessary. This is not desirable, because an undesired current flowing in each standard cell (e.g. through current peculiar to CMOS circuits) increases more than necessary and it causes power consumption to be increased. The through current can also be a cause of generating noise on a power supply line in a semiconductor integrated circuit device, and therefore, in an analog-digital mixed integrated circuit device having an analog circuit mounted on the same substrate, an increase in the through current adversely affects circuit operation and circuit property.
The aforementioned problem of an increase in power consumption and noise also arises when a semiconductor integrated circuit designed on the assumption that it is operated at some clock frequency is operated at a frequency lower than the assumed frequency. Additionally, the same problem as the above can also arise in an integrated circuit device using a transistor of a fixed size such as a gate array, and reusing an existing logic cell such as a multiplier and a memory in another integrated circuit.
The above described problems will be described more specifically with reference to a CMOS inverter shown in FIG. 1 by way of an example.
A CMOS inverter 4 shown in FIG. 11 is structured by a P channel MOS field effect transistor 5 (a field effect transistor is simply referred to as a transistor hereinafter) and an N channel MOS transistor 6. Connected in series, P channel MOS transistor 5 and N channel MOS transistor 6 are interposed between a power supply 7 (its voltage value is Vdd) and a ground GND. Each gate of P channel MOS transistor 5 and N channel MOS transistor 6 is connected to an input terminal 8. A connecting point of the drain of P channel MOS transistor 5 and the drain of N channel MOS transistor 6 is connected to an output terminal 9. CMOS inverter 4 having such a configuration has a load capacitance Co at its output terminal 9. This load capacitance Co is a sum of an interconnection capacitance and an input capacitance at the next stage.
FIG. 12 is a graph showing an input/output property of the CMOS inverter shown in FIG. 11. The through current of CMOS inverter 4 is shown with broken lines in FIG.12. Because each threshold voltage of P channel MOS transistor 5 and N channel MOS transistor 6 is generally about 1 V when an input voltage is within a range of from 1 V to (Vdd-1) V, P channel MOS transistor 5 and N channel MOS transistor 6 are both turned on and in addition to a current necessary to charge and discharge load capacitance Co, another current flows from power supply 7 to ground GND through a series circuit of P channel MOS transistor 5 and N channel MOS transistor 6. This current is referred to a through current. A charging current of the load capacitance, a discharging current of the load capacitance and through current are all proportional to the transistor sizes W/L of P channel MOS transistor 5 and N channel MOS transistor 6. W is a channel width of a transistor. L is a channel length of a transistor. As a value of W/L becomes higher, each ON resistance of P channel MOS transistor 5 and N channel MOS transistor 6 becomes smaller, which allows more current to flow.
Therefore, if each of transistors 5 and 6 is designed to have a high value of a transistor size W/L on the assumption that load capacitance Co is that of the worst case, a value of the through current naturally becomes high. However, when load capacitance Co becomes smaller than that of the worst case as a consequence of automatic arranging and interconnecting, the through current becomes undesirably small and wasteful power consumption increases.
When CMOS inverter 4, which is designed to charge and discharge load capacitance Co sufficiently when it is operated with some clock frequency (e.g. 20 MHz), is operated with a clock frequency (e.g. 10 MHz) lower than the frequency determined at the time of designing, each transistor size W/L of each of transistors 5 and 6 is larger than necessary, and therefore through current becomes undesirably too large. Because driving capability of CMOS inverter 4 becomes also greater than necessary, rise/fall of an output waveform of CMOS inverters 4 is sharper than necessary. The sharp change of the output waveform is not desirable because it tends to cause the generation of noise such as ringing and therefore malfunction of the circuit.
As described above, in a conventional semiconductor integrated circuit device, a problem exists that there is a case where driving capability of a logic cell becomes greater than necessary, so that power consumption and noise are increased.